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1. general description the PCA9512A is a hot swappable i 2 c-bus and smbus buffer that allows i/o card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 v and 5 v systems while maintaining the best noise margin for each voltage level. either pin may be powered with supply voltages ranging from 2.7 v to 5.5 v with no constraints on which supply voltage is higher. control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. when the connection is made, the PCA9512A provides bidirectional buffering, keeping the backplane and card capacitances isolated. the PCA9512A rise time accelerator circuitry allows the use of weaker dc pull-up currents while still meeting rise time requirements. the PCA9512A incorporates a digital input pin that enables and disables the rise time accelerators on all four sdan and scln pins. during insertion, the PCA9512A sdan and scln pins are precharged to 1 v to minimize the current required to charge the parasitic capacitance of the chip. the dynamic offset design of the pca9510a/11a/12a/13a/14a i/o drivers allow them to be connected to another pca9510a/11a/12a/13a/14a device in series or in parallel and to the a side of the pca9517. the pca9510a/11a/12a/13a/14a cannot connect to the static offset i/os used on the pca9515/15a/16/16a/18, pca9517 b side, or p82b96 sx/y side. 2. features n bidirectional buffer for sda and scl lines increases fanout and prevents sda and scl corruption during live board insertion and removal from multi-point backplane systems n compatible with i 2 c-bus standard mode, i 2 c-bus fast mode, and smbus standards n built-in d v/ d t rise time accelerators on all sdan and scln pins (0.6 v threshold) with ability to disable d v/ d t rise time accelerator through the acc pin for lightly loaded systems n 5 v to 3.3 v level translation with optimum noise margin n high-impedance sdan and scln pins for v cc or v cc2 =0v n 1 v precharge on all sdan and scln pins n supports clock stretching and multiple master arbitration and synchronization n operating power supply voltage range: 2.7 v to 5.5 v n i/os are not 5.5 v tolerant n 0 hz to 400 khz clock frequency PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer rev. 01 7 october 2005 product data sheet
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 2 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n packages offered: so8, tssop8 (msop8) 3. applications n cpci, vme, advancedtca cards and other multi-point backplane cards that are required to be inserted or removed from an operating system 4. feature selection 5. ordering information [1] also known as msop8. standard packing quantities and other packaging data are available at the philips website. table 1: feature selection chart feature pca9510a pca9511a PCA9512A pca9513a pca9514a idle detect yes yes yes yes yes high-impedance sdan, scln pins for v cc = 0 v yes yes yes yes yes rise time accelerator circuitry on sdan and scln pins - yes yes yes yes rise time accelerator circuitry hardware disable pin for lightly loaded systems --yes-- rise time accelerator threshold 0.8 v versus 0.6 v improves noise margin ---yesyes ready open-drain output yes yes - yes yes tw o v cc pins to support 5 v to 3.3 v level translation with improved noise margins --yes-- 1 v precharge on all sdan and scln pins in only yes yes - - 92 m a current source on sclin and sdain for picmg applications ---yes- table 2: ordering information t amb = - 40 c to +85 c type number topside mark package name description version PCA9512Ad pa9512a so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 PCA9512Adp 9512a tssop8 [1] plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 3 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 6. block diagram fig 1. block diagram of PCA9512A 002aab788 100 k w rch3 1 volt precharge 100 k w rch4 100 k w rch1 100 k w rch2 connect backplane-to-card connection slew rate detector slew rate detector connect connect 2 ma 2 ma backplane-to-card connection slew rate detector slew rate detector connect connect 2 ma 2 ma sdain sclin 0.5 pf sclout rd s qb uvlo 20 pf 0.55v cc / 0.45v cc 0.5 m a stop bit and bus idle 0.55v cc / 0.45v cc 100 m s delay uvlo sdaout v cc2 connect gnd PCA9512A v cc acc connect acc acc
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 4 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 7. pinning information 7.1 pinning 7.2 pin description 8. functional description refer to figure 1 bloc k diag r am of PCA9512A . 8.1 start-up when the PCA9512A is powered up, either v cc or v cc2 may rise ?rst and either may be more positive or they may be equal, however the PCA9512A will not leave the undervoltage lock out or initialization state until both v cc and v cc2 have gone above 2.5 v. if either v cc or v cc2 drops below 2.0 v it will return to the undervoltage lock out state. in the undervoltage lock out state the connection circuitry is disabled, the rise time accelerators are disabled, and the precharge circuitry is also disabled. after both v cc and v cc2 are valid, independent of which is higher, the PCA9512A enters the initialization state; during this state the 1 v precharge circuitry is activated and pulls up the sdan and scln pins to 1 v through individual 100 k w nominal resistors. at the end of the initialization state the stop bit and bus idle detect circuit is enabled. when all the sdan and scln pins have been high for the bus idle time or when all pins are high and a fig 2. pin con?guration for so8 fig 3. pin con?guration for tssop8 v cc2 v cc sclout sdaout sclin sdain gnd acc 002aab789 1 2 3 4 6 5 8 7 PCA9512Ad PCA9512Adp v cc2 v cc sclout sdaout sclin sdain gnd acc 002aab790 1 2 3 4 6 5 8 7 table 3: pin description symbol pin description v cc2 1 supply voltage for devices on the card i 2 c-buses. connect pull-up resistors from sdaout and sclout to this pin. sclout 2 serial clock output to and from the scl bus on the card sclin 3 serial clock input to and from the scl bus on the backplane gnd 4 ground supply; connect this pin to a ground plane for best results. acc 5 cmos threshold digital input pin that enables and disables the rise time accelerators on all four sdan and scln pins. acc enables all accelerators when set to v cc2 , and turns them off when set to gnd. sdain 6 serial data input to and from the sda bus on the backplane sdaout 7 serial data output to and from the sda bus on the card v cc 8 supply voltage; from the backplane, connect pull-up resistors from sdain and sclin to this pin.
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 5 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer stop condition is seen on the sdain and sclin pins, the connect circuitry is activated, connecting sdain to sdaout and sclin to sclout. the 1 v precharge circuitry is disabled when the connection is made, unless the acc pin is low; the rise time accelerators are enabled at this time also. 8.2 connect circuitry once the connection circuitry is activated, the behavior of sdain and sdaout as well as sclin and sclout become identical, with each acting as a bidirectional buffer that isolates the input bus capacitance from the output bus capacitance while communicating. if v cc 1 v cc2 , then a level shifting function is performed between input and output. a low forced on either sdain or sdaout will cause the other pin to be driven to a low by the PCA9512A. the same is also true for the scln pins. noise between 0.7v cc and v cc on the sdain and sclin pins, and 0.7v cc2 and v cc2 on the sdaout and sclout pins is generally ignored because a falling edge is only recognized when it falls below 0.7v cc for sdain and sclin (or 0.7v cc2 for sdaout and sclout pins) with a slew rate of at least 1.25 v/ m s. when a falling edge is seen on one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small voltage above the falling pin. the driver will pull the pin down at a slew rate determined by the driver and the load. the ?rst falling pin may have a fast or slow slew rate; if it is faster than the pull-down slew rate, then the initial pull-down rate will continue until it is low. if the ?rst falling pin has a slow slew rate, then the second pin will be pulled down at its initial slew rate only until it is just above the ?rst pin voltage then they will both continue down at the slew rate of the ?rst. once both sides are low they will remain low until all the external drivers have stopped driving lows. if both sides are being driven low to the same (or nearly the same) value by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving, that pin will rise and rise above the nominal offset voltage until the internal driver catches up and pulls it back down to the offset voltage. this bounce is worst for low capacitances and low resistances, and may become excessive. when the last external driver stops driving a low, that pin will bounce up and settle out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the rc time constant. as long as the slew rate is at least 1.25 v/ m s, when the pin voltage exceeds 0.6 v, the rise time accelerator circuits are turned on and the pull-down driver is turned off. if the acc pin is low, the rise time accelerator circuits will be disabled, but the pull-down driver will still turn off. 8.3 maximum number of devices in series each buffer adds about 0.1 v dynamic level offset at 25 c with the offset larger at higher temperatures. maximum offset (v offset ) is 0.150 v with a 10 k w pull-up resistor. the low level at the signal origination end (master) is dependent upon the load and the only speci?cation point is the i 2 c-bus speci?cation of 3 ma will produce v ol < 0.4 v, although if lightly loaded the v ol may be ~ 0.1 v. assuming v ol = 0.1 v and v offset = 0.1 v, the level after four buffers would be 0.5 v, which is only about 0.1 v below the threshold of the rising edge accelerator (about 0.6 v). with great care a system with four buffers may work, but as the v ol moves up from 0.1 v, noise or bounces on the line will result in ?ring the rising edge accelerator thus introducing false clock edges. generally it is recommended to limit the number of buffers in series to two, and to keep the load light to minimize the offset.
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 6 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer the pca9510a (rise time accelerator is permanently disabled) and the PCA9512A (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns on the accelerator turns the pull-down off. if the v il is above ~ 0.6 v and a rising edge is detected, the pull-down will turn off and will not turn back on until a falling edge is detected. consider a system with three buffers connected to a common node and communication between the master and slave b that are connected at either end of buffer a and buffer b in series as shown in figure 4 . consider if the v ol at the input of buffer a is 0.3 v and the v ol of slave b (when acknowledging) is 0.4 v with the direction changing from master to slave b and then from slave b to master. before the direction change you would observe v il at the input of buffer a of 0.3 v and its output, the common node, is ~ 0.4 v. the output of buffer b and buffer c would be ~ 0.5 v, but slave b is driving 0.4 v, so the voltage at slave b is 0.4 v. the output of buffer c is ~ 0.5 v. when the master pull-down turns off, the input of buffer a rises and so does its output, the common node, because it is the only part driving the node. the common node will rise to 0.5 v before buffer b's output turns on, if the pull-up is strong the node may bounce. if the bounce goes above the threshold for the rising edge accelerator ~ 0.6 v the accelerators on both buffer a and buffer c will ?re contending with the output of buffer b. the node on the input of buffer a will go high as will the input node of buffer c. after the common node voltage is stable for a while the rising edge accelerators will turn off and the common node will return to ~ 0.5 v because the buffer b is still on. the voltage at both the master and slave c nodes would then fall to ~ 0.6 v until slave b turned off. this would not cause a failure on the data line as long as the return to 0.5 v on the common node ( ~ 0.6 v at the master and slave c) occurred before the data setup time. if this were the scl line, the parts on buffer a and buffer c would see a false clock rather than a stretched clock, which would cause a system error. 8.4 propagation delays the delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. if the pull-up currents are the same, any difference in rise time is directly proportional to the difference in capacitance between the two sides. the t plh may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. the t phl can never be negative because the output does not start to fall until the input is below 0.7v cc (or 0.7v cc2 for sdaout and sclout), and the output turn on has a non-zero delay, and the output has a limited maximum slew rate, and even if the input slew fig 4. system with 3 buffers connected to common node 002aab581 buffer c buffer b buffer a common node slave b slave c master
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 7 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer rate is slow enough that the output catches up it will still lag the falling voltage of the input by the offset voltage. the maximum t phl occurs when the input is driven low with zero delay and the output is still limited by its turn-on delay and the falling edge slew rate. the output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature, v cc or v cc2 and process, as well as the load current and the load capacitance. 8.5 rise time accelerators during positive bus transactions, a 2 ma current source is switched on to quickly slew the sda and scl lines high once the input level of 0.6 v for the PCA9512A is exceeded. the rising edge rate should be at least 1.25 v/ m s to guarantee turn on of the accelerators. 8.6 acc boost current enable users having lightly loaded systems may wish to disable the rise time accelerators. driving this pin to ground turns off the rise time accelerators on all four sdan and scln pins. driving this pin to the v cc2 voltage enables normal operation of the rise time accelerators. 8.7 resistor pull-up value selection the system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 v/ m s on the sdan and scln pins, in order to activate the boost pull-up currents during rising edges. choose maximum resistor value using the formula: where r pu is the pull-up resistor value in w , v cc(min) is the minimum v cc voltage in volts, and c is the equivalent bus capacitance in picofarads. in addition, regardless of the bus capacitance, always choose r pu 16 k w for v cc = 5.5 v maximum, r pu 24 k w for v cc = 3.6 v maximum. the start-up circuitry requires logic high voltages on sdaout and sclout to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. see the curves in figure 5 and figure 6 for guidance in resistor pull-up selection. r pu 800 10 3 v cc min () 0.6 C c ----------------------------------- ? ??
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 8 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 8.8 hot swapping and capacitance buffering application figure 7 through figure 9 illustrate the usage of the PCA9512A in applications that take advantage of both its hot swapping and capacitance buffering features. in all of these applications, note that if the i/o cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise time and fall time requirements dif?cult to meet. placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. for a given i/o card, the PCA9512A drives the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pf, the connector, trace, and all additional cards on the backplane. see application note an10160, hot swap bus buffer for more information on applications and technical assistance. fig 5. bus requirements for 3.3 v systems fig 6. bus requirements for 5 v systems c b (pf) 0 400 300 100 200 002aab582 10 20 30 r pu (k w ) 0 recommended pull-up rise time > 300 ns r max = 24 k w c b (pf) 0 400 300 100 200 002aab583 10 5 15 20 r pu (k w ) 0 recommended pull-up rise time > 300 ns r max = 16 k w
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 9 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer remark: application assumes bus capacitance within proper operation region of figure 5 and figure 6 . fig 7. hot swapping multiple i/o cards into a backplane using the PCA9512A in a cpci, vme, and advancedtca system 002aab791 r4 10 k w c1 0.01 m f sdaout sclout acc v cc2 gnd r5 10 k w r6 10 k w v cc sdain sclin power supply hot swap card1_sda card1_scl staggered connector i/o peripheral card 1 backplane connector r2 10 k w r1 10 k w v cc2 backplane bd_sel sda scl v cc r3 5.1 w c2 0.01 m f PCA9512A r8 10 k w c3 0.01 m f sdaout sclout acc v cc2 gnd r9 10 k w r10 10 k w v cc sdain sclin power supply hot swap card2_sda card2_scl staggered connector i/o peripheral card 2 r7 5.1 w c4 0.01 m f PCA9512A r12 10 k w c5 0.01 m f sdaout sclout acc v cc2 gnd r13 10 k w r14 10 k w v cc sdain sclin power supply hot swap cardn_sda cardn_scl staggered connector i/o peripheral card n r11 5.1 w c6 0.01 m f PCA9512A
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 10 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer remark: application assumes bus capacitance within proper operation region of figure 5 and figure 6 . fig 8. hot swapping multiple i/o cards into a backplane using the PCA9512A with a custom connector 002aab792 r4 10 k w c1 0.01 m f sdaout sclout acc v cc2 gnd r5 10 k w r6 10 k w v cc sdain sclin card1_sda card1_scl staggered connector i/o peripheral card 1 backplane connector r2 10 k w r1 10 k w v cc2 backplane sda scl v cc r3 5.1 w c2 0.01 m f PCA9512A r8 10 k w c3 0.01 m f sdaout sclout acc v cc2 gnd r9 10 k w r10 10 k w v cc sdain sclin card2_sda card2_scl staggered connector i/o peripheral card 2 r7 5.1 w c4 0.01 m f PCA9512A remark: application assumes bus capacitance within proper operation region of figure 5 and figure 6 . fig 9. 5 v to 3.3 v level translator and bus buffer 002aab793 r4 10 k w c2 0.01 m f sdaout sclout acc v cc gnd sdain sclin r1 10 k w v cc (5 v) sda scl r3 10 k w r2 10 k w card_sda card_scl v cc2 c1 0.01 m f PCA9512A card_v cc (3 v)
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 11 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 9. application design-in information 10. limiting values [1] card side supply voltage. [2] maximum current for inputs. [3] maximum current for i/o pins. fig 10. typical application 002aab794 acc gnd r5 10 k w r3 10 k w r4 10 k w sdaout sclout c2 0.01 m f r1 10 k w r2 10 k w v cc (5 v) sdain sclin PCA9512A sda scl v cc v cc2 c1 0.01 m f card_v cc (3 v) card_sda card_scl table 4: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 0.5 +7 v v cc2 supply voltage 2 [1] - 0.5 +7 v v n voltage on any other pin - 0.5 +7 v i i input current [2] - 20 ma i i/o input/output current [3] - 50 ma t oper operating temperature - 40 +85 c t stg storage temperature - 65 +125 c t sp solder point temperature 10 s maximum - 300 c t j(max) maximum junction temperature - 125 c
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 12 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 11. characteristics table 5: characteristics v cc = 2.7 v to 5.5 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit power supply v cc supply voltage [1] 2.7 - 5.5 v v cc2 supply voltage 2 [2] [1] 2.7 - 5.5 v i cc supply current v cc = 5.5 v; v sdain =v sclin =0v - 1.8 3.6 ma i cc2 supply current 2 v cc = 5.5 v; v sdaout =v sclout =0v - 1.7 2.9 ma start-up circuitry v pch precharge voltage sda, scl ?oating [1] 0.8 1.1 1.2 v t en enable time on power-up [3] - 180 - m s t idle idle time [1] [4] 50 140 250 m s rise time accelerators i trt(pu) transient boosted pull-up current positive transition on sda, scl; v acc = 0.7 v cc2 ; v cc = 2.7 v; slew rate = 1.25 v/ m s [5] 12-ma v th(dis)(acc) disable threshold voltage on pin acc 0.3v cc2 0.5v cc2 -v v th(en)(acc) enable threshold voltage on pin acc - 0.5v cc2 0.7v cc2 v i i(acc) input current on pin acc - 1 0.1 +1 m a t pd(on/off)(acc) on/off propagation delay on pin acc -5-ns input-output connection v offset offset voltage 10 k w to v cc on sda, scl; v cc = 3.3 v; v cc2 = 3.3 v; v i = 0.2 v [1] [6] 0 115 175 mv c i input capacitance digital; guaranteed by design, not subject to test - - 10 pf v ol low-state output voltage v i = 0 v; sdan, scln pins; i sink = 3 ma; v cc = 2.7 v; v cc2 = 2.7 v [1] 0 0.3 0.4 v i li input leakage current sdan, scln pins; v cc = 5.5 v; v cc2 = 5.5 v - 1-+1 m a
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 13 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer [1] this speci?cation applies over the full operating temperature range. [2] card side supply voltage. [3] the enable time is from power-up of v cc and v cc2 3 2.7 v to when idle or stop time begins. [4] idle time is from when sdan and scln are high after enable time has been met. [5] i trt(pu) varies with temperature and v cc voltage, as shown in section 11.1 t ypical perf or mance char acter istics . [6] the connection circuitry always regulates its output to a higher voltage than its input. the magnitude of this offset voltage as a function of the pull-up resistor and v cc voltage is shown in section 11.1 t ypical perf or mance char acter istics . [7] guaranteed by design, not production tested. [8] c b = total capacitance of one bus line in pf. system characteristics f scl scl clock frequency [7] 0 - 400 khz t buf bus free time between stop condition and start condition [7] 1.3 - - m s t hd;sta start condition hold time [7] 0.6 - - m s t su;sta start condition (or repeated start condition) set-up time [7] 0.6 - - m s t su;sto stop condition set-up time [7] 0.6 - - m s t hd;dat data hold time [7] 300 - - ns t su;dat data set-up time [7] 100 - - ns t low scl low time [7] 1.3 - - m s t high scl high time [7] 0.6 - - m s t f fall time sda and scl [7] [8] 20 + 0.1 c b - 300 ns t r rise time sda and scl [7] [8] 20 + 0.1 c b - 300 ns table 5: characteristics continued v cc = 2.7 v to 5.5 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 14 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 11.1 typical performance characteristics i cc2 (pin 1) typical current averages 0.1 ma less than i cc on pin 8. fig 11. i cc versus temperature fig 12. i trt(pu) versus temperature c i =c o > 100 pf; r pu(in) =r pu(out) =10k w v cc = 3.3 v or 5.5 v fig 13. input/output t phl versus temperature fig 14. connection circuitry v o - v i t amb ( c) - 40 +90 +25 002aab795 1.95 2.15 i cc (ma) 1.35 v cc = 5.5 v 3.3 v 2.7 v 1.75 1.55 t amb ( c) - 40 +90 +25 002aab796 4 8 12 i trt(pu) (ma) 0 3.3 v v cc = 5 v 2.7 v t amb ( c) - 40 +90 +25 002aab589 70 80 90 t phl (ns) 60 3.3 v v cc = 5.5 v 2.7 v r pu (k w ) 040 30 10 20 002aab591 150 250 350 v o - v i (mv) 50 v cc = 5 v 3.3 v
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 15 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 12. test information r l = load resistor c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to the output impedance z o of the pulse generator fig 15. test circuitry for switching times pulse generator v o c l 100 pf r l 10 k w 002aab595 r t v i v cc v cc d.u.t.
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 16 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 13. package outline fig 16. package outline sot96-1 (so8) unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 17 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer fig 17. package outline sot505-1 (tssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.70 0.35 6 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot505-1 99-04-09 03-02-18 w m b p d z e 0.25 14 8 5 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 1.1 pin 1 index
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 18 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 14. soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 14.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 19 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 14.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 6: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 20 of 22 philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 15. abbreviations 16. revision history table 7: abbreviations acronym description advancedtca advanced telecommunications computing architecture cdm charged device model cpci compact peripheral component interface esd electrostatic discharge hbm human body model i 2 c-bus inter ic bus mm machine model pci peripheral component interface picmg pci industrial computer manufacturers group smbus system management bus vme versamodule eurocard table 8: revision history document id release date data sheet status change notice doc. number supersedes PCA9512A_1 20051007 product data sheet - - -
philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer PCA9512A_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 7 october 2005 21 of 22 17. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 19. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 20. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of koninklijke philips electronics n.v. 21. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 7 october 2005 document number: PCA9512A_1 published in the netherlands philips semiconductors PCA9512A level shifting hot swappable i 2 c-bus and smbus bus buffer 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 feature selection . . . . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 4 8.1 start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8.2 connect circuitry. . . . . . . . . . . . . . . . . . . . . . . . 5 8.3 maximum number of devices in series . . . . . . . 5 8.4 propagation delays . . . . . . . . . . . . . . . . . . . . . . 6 8.5 rise time accelerators . . . . . . . . . . . . . . . . . . . 7 8.6 acc boost current enable. . . . . . . . . . . . . . . . . 7 8.7 resistor pull-up value selection . . . . . . . . . . . . 7 8.8 hot swapping and capacitance buffering application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 application design-in information . . . . . . . . . 11 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 11.1 typical performance characteristics . . . . . . . . 14 12 test information . . . . . . . . . . . . . . . . . . . . . . . . 15 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 14.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 14.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 14.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 19 14.5 package related soldering information . . . . . . 19 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 17 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 21 18 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 19 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 20 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 contact information . . . . . . . . . . . . . . . . . . . . 21

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